1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and a digital camera comprising the same, and more specifically, it relates to a semiconductor integrated circuit having a large-scale macro cell part such as a CPU and a digital camera comprising the same.
2. Description of the Prior Art
An ASIC (application specific integrated circuit) readily implementing a device for a specific application with CAD (computer aided design) is known in general. As to a method of designing such an ASIC, a gate array system, a standard cell system and an embedded array system are generally known as methods of efficiently designing semicustom LSIs.
In the gate array system, basic cells covered with transistors in an arrayed manner are arranged and wired for forming a logic circuit. The gate array system requires only a wiring step as the fabrication step, and hence a TAT (turnaround time) between completion of design and trial manufacture of a sample is advantageously reduced.
In the standard cell system, optimally designed verified logic circuit cells and a macro cell part are previously registered in a CAD database and arbitrarily combined with each other through CAD. However, this standard cell system employs a mask specific to a type from a transistor forming step, and hence fabrication cannot be started until the design is completed. In the standard cell system, therefore, the TAT is inconveniently lengthened as compared with the gate array system. On the other hand, a large-scale macro cell part such as a CPU or a memory can advantageously be readily designed in this standard cell system.
The embedded array system adopts advantages of the gate array system and the standard cell system. An embedded array employed in the embedded array system has a structure obtained by embedding a macro cell part of standard cells in a random logic part of a gate array. After deciding the number of gates of the random logic part and the type of the embedded macro cell part, fabrication of a wafer is immediately started to advance fabrication of the embedded array up to a stage preceding a wiring step. Completion of logical design is waited in this state. After termination of a logic simulation, an LSI is completed by simply wiring the random logic part.
In the embedded array system, the macro cell part of the standard cells is previously registered and hence parts other than the macro cell part are designed. Therefore, the macro cell part of the standard cells may not be embodied to a transistor unit level and hence the TAT can be reduced for the standard cells. Further, circuits forming the random logic part can be changed only through the wiring step.
When designing the aforementioned conventional ASIC, power supply wires (a power supply potential line and a ground potential line) are necessary for fixing signal lines in the circuit to a power supply potential and a ground potential. In a technique disclosed in Japanese Patent Laying-Open No. 8-125025 (1996), for example, a main power supply potential line (power supply trunk) and a main ground potential line (ground trunk) serving as main power supply wires are provided in the form of rings enclosing a microcomputer core serving as a macro cell part in design of an ASIC microcomputer. The microcomputer core is provided therein with an auxiliary power supply potential line (power supply wire) and an auxiliary ground potential line (ground wire) for electrically connecting the main power supply potential line and the main ground potential line set outside the region of the microcomputer core with elements provided in the microcomputer core.
In the aforementioned conventional structure, however, the main power supply potential line and the main ground potential line present outside the region of the microcomputer core serving as the macro cell part disadvantageously inhibit reduction of the area of the circuit.
In particular, a large quantity of current flows through the main power supply potential line and the main ground potential line for supplying a power supply potential and a ground potential to the overall microcomputer core. Therefore, the main power supply potential line and the main ground potential line must be increased in width in order to prevent electromigration a voltage drop resulting from wire resistance. Such wide main power supply wires (the main power supply potential line and the main ground potential line) are generally set outside the region of the microcomputer core, and hence the circuit area is disadvantageously increased.
An object of the present invention is to provide a semiconductor integrated circuit capable of saving the area.
Another object of the present invention is to improve a margin for wiring in a macro cell part of a semiconductor integrated circuit.
Still another object of the present invention is to increase the degree of freedom in layout of internal wires in a macro cell part of a semiconductor integrated circuit and improving wiring efficiency for the internal wires.
A further object of the present invention is to provide a digital camera comprising the aforementioned semiconductor integrated circuit.
A semiconductor integrated circuit according to an aspect of the present invention comprises a macro cell part having a plurality of wiring layers, an internal wire of the macro cell part formed by the wiring layers of the macro cell part and a main power supply wire formed by the wiring layers of the macro cell part and arranged in the region of the macro cell part. In the semiconductor integrated circuit according to this aspect, the main power supply wire is so arranged in the region of the macro cell part that the area of the circuit can be saved as compared with the conventional case of arranging the main power supply wire outside the region of the macro cell part.
In the semiconductor integrated circuit according to the aforementioned aspect, the main power supply wire preferably includes a plurality of first main power supply wires formed by the same wiring layer. In this case, the main power supply wire preferably includes a second main power supply wire connecting the first main power supply wires with each other.
In the semiconductor integrated circuit according to the aforementioned aspect, the macro cell part preferably has a multilayer wiring structure, and the main power supply wire is formed by an arbitrary wiring layer of multilayer wiring in the macro cell part. The semiconductor integrated circuit further comprises a connection wiring layer formed by another wiring layer of multilayer wiring in the macro cell part and electrically connected with the main power supply wire. When the macro cell part has a multilayer wiring structure in the aforementioned manner, a margin for wiring in the macro cell part can be improved. Consequently, the main power supply wire can be readily arranged in the region of the macro cell part.
In this case, the main power supply wire and the connection wiring layer are preferably connected with each other by a connection hole wire. More preferably, the main power supply wire and the connection wiring layer are connected with each other by at least two connection hole wires. When connecting the main power supply wire and the connection wiring layer with each other by at least two connection hole wires as described above, resistance between the main power supply wire and the connection wiring layer is reduced as compared with the case of connecting the same by a single connection hole wire, and hence a voltage drop across the main power supply wire and the connection wiring layer can be reduced. The width of the connection wiring layer is preferably substantially equal to the width of the main power supply wire. In this case, at least two connection hole wires can be readily formed between the connection wiring layer having a width substantially identical to that of the wide main power supply wire and the main power supply wire. Consequently, a voltage drop across the main power supply wire and the connection wiring layer can be readily reduced.
In this case, the macro cell part preferably includes a cell string having a semiconductor element, and the cell string having the semiconductor element is arranged under the main power supply wire. When the macro cell part has a multilayer wiring structure as described above, the cell string having the semiconductor element can be arranged under the main power supply wire. Consequently, signal lines between such cell strings can be readily connected with no hindrance by the main power supply wire. In this case, the macro cell part preferably includes a cell region consisting of a plurality of cell strings, an auxiliary power supply wire is preferably connected to the main power supply wire through the connection wiring layer, and the auxiliary power supply wire is preferably formed to extend along the longitudinal direction of the cell strings of the cell region.
Preferably, the main power supply wire includes a plurality of first main power supply wires prepared from a first wiring layer and a second main power supply wire prepared from a second wiring layer for connecting the first main power supply wires with each other. In this case, the macro cell part preferably has at least three wiring layers, for forming either the first main power supply wires or the second main power supply wire by the uppermost wiring layer while forming either the second main power supply wire or the first main supply wires by the wiring layer next to the uppermost wiring layer. Thus, signal lines between the cell strings can be readily connected with each other through the third and subsequent wiring layers with no hindrance by the main power supply wire.
In the semiconductor integrated circuit according to the aforementioned aspect, the main power supply wire preferably includes at least one of a high-potential side main power supply wire and a low-potential side main power supply wire. In this case, the high-potential side main power supply wire preferably includes a main power supply potential line, and the low-potential side main power supply wire preferably includes a main ground potential line.
In the semiconductor integrated circuit according to the aforementioned aspect, the main power supply wire is preferably at least partially subdivided. When the main power supply wire is at least partially subdivided, the width of the main power supply wire is reduced in the subdivided region. Thus, the degree of freedom in layout of the internal wires of the macro cell part is increased in the region as compared with a main power supply wire having a large width. Consequently, wiring efficiency for the internal wires of the macro cell part can be improved in the subdivided region of the main power supply wire.
In this case, a connection wiring layer is preferably connected to each of a plurality of subdivided main power supply wires. Further, an auxiliary power supply wire is preferably connected in common to the plurality of subdivided main power supply wires through the connection wiring layer. When connecting the auxiliary power supply wire in common to the plurality of subdivided main power supply wires through the connection wiring layer, the length of the auxiliary power supply wire connected between adjacent main power supply wires is reduced as compared with a main power supply wire not subdivided in the aforementioned manner. Thus, resistance of the auxiliary power supply wire is reduced between the main power supply wires. Consequently, a voltage drop across the main power supply wires can be reduced.
The plurality of subdivided main power supply wires are preferably arranged substantially at regular intervals. When arranging the main power supply wires substantially at regular intervals, dispersion of potentials caused by a voltage drop can be suppressed over the entire subdivided regions of the main power supply wires. Consequently, a malfunction resulting from a local voltage drop can be suppressed.
In this case, the macro cell part preferably includes a cell region of a standard cell system, and the main power supply wire is preferably subdivided in the cell region of the standard cell system. The macro cell part may include a cell region of a gate array system, and the main power supply wire may be subdivided in the cell region of the gate array system.
Preferably, the main power supply wire includes a plurality of first main power supply wires prepared from the same wiring layer. In this case, the main power supply wire preferably includes a second main power supply wire connecting the first main power supply wires with each other. The main power supply wire may include a third main power supply wire for connecting a plurality of subdivided parts of the main power supply wire with each other.
Preferably, the macro cell part has a multilayer wiring structure, and the main power supply wire is formed by an arbitrary wiring layer of multilayer wiring in the macro cell part. The semiconductor integrated circuit further comprises a connection wiring layer formed by another wiring layer of multilayer wiring in the macro cell part and electrically connected with the main power supply wire. When the macro cell part has a multilayer wiring structure in the aforementioned manner, a margin for wiring in the macro cell part can be improved. Consequently, the main power supply wire can be readily arranged in the region of the macro cell part.
In this case, the main power supply wire and the connection wiring layer are preferably connected with each other by a connection hole wire. Further, the macro cell part preferably includes a cell string having a semiconductor element, and the cell string having the semiconductor element is preferably arranged under the main power supply wire. When the macro cell part has a multilayer wiring structure as described above, the cell string having the semiconductor element can be arranged under the main power supply wire. Consequently, signal lines between such cell strings can be readily connected with no hindrance by the main power supply wire. In this case, the macro cell part preferably includes a cell region consisting of a plurality of cell strings, the main power supply wire is preferably subdivided in the cell region, an auxiliary power supply wire is preferably connected in common to the subdivided main power supply wire through the connection wiring layer, and the auxiliary power supply wire is preferably formed to extend along the longitudinal direction of the cell strings of the cell region.
In this case, the main power supply wire preferably includes a plurality of first main power supply wires prepared from a first wiring layer and a second main power supply wire prepared from a second wiring layer for connecting the first main power supply wires with each other. In this case, the macro cell part preferably has at least three wiring layers, for forming either the first main power supply wires or the second main power supply wire by the uppermost wiring layer while forming either the second main power supply wire or the first main supply wires by the wiring layer next to the uppermost wiring layer. Thus, signal lines between the cell strings can be readily connected with each other through the third and subsequent wiring layers with no hindrance by the main power supply wire.
Preferably, the main power supply wire includes at least one of a high-potential side main power supply wire and a low-potential side main power supply wire. In this case, the high-potential side main power supply wire preferably includes a main power supply potential line, and the low-potential side main power supply wire preferably includes a main ground potential line.
A digital camera according to another aspect of the present invention comprises a semiconductor integrated circuit including a macro cell part having a plurality of wiring layers, an internal wire of the macro cell part formed by the wiring layers of the macro cell part and a main power supply wire formed by the wiring layers of the macro cell part and arranged in the region of the macro cell part. In the digital camera according to this aspect comprising the semiconductor integrated circuit having the main power supply wire arranged in the region of the macro cell part, the area of the circuit forming the digital camera can be saved as compared with such a conventional case that the main power supply wire is arranged outside the region of the macro cell part.
A digital camera according to still another aspect of the present invention comprises a semiconductor integrated circuit including a macro cell part having a plurality of wiring layers, an internal wire of the macro cell part formed by the wiring layers of the macro cell part and a main power supply wire formed by the wiring layers of the macro cell part, arranged in the region of the macro cell part and at least partially subdivided. In the digital camera according to this aspect, the main power supply wire arranged in the region of the macro cell part is at least partially subdivided so that the width of the main power supply wire is reduced in the subdivided region. Thus, the degree of freedom in layout of the internal wire of the macro cell part is increased in this region as compared with a main power supply wire having a large width. Consequently, wiring efficiency for the internal wire of the macro cell part can be improved in the subdivided region of the main power supply wire. Thus, a digital camera including a macro cell part having high wiring efficiency can be provided.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.